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16 Mbit Concurrent SuperFlash
SST36VF1601
SST36V160116Mb (x16) Concurrent SuperFlash
Data Sheet
FEATURES:
* Organized as 1M x16 * Dual Bank Architecture for Concurrent Read/Write Operation - 16 Mbit Bottom Sector Protection - SST36VF1601: 12 Mbit + 4 Mbit * Single 2.7-3.6V for Read and Write Operations * Superior Reliability - Endurance: 100,000 cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 25 mA - Standby Current: 4 A * Hardware Sector Protection/WP# Input Pin - Protects 4 outermost sectors (4 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high * Hardware Reset Pin (RST#) - Resets the internal state machine to reading array data * Sector-Erase Capability - Uniform 1 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Fast Read Access Time - 70 ns * Latched Address and Data * Fast Erase and Word-Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 70 ms - Word-Program Time: 14 s - Chip Rewrite Time: 8 seconds * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * Conforms to Common Flash Memory Interface (CFI) * JEDEC Standards - Flash EEPROM Pinouts and command sets * Packages Available - 48-lead TSOP (12mm x 20mm) - 48-ball TFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST36VF1601 is 1M x16 CMOS Concurrent Read/ Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.The SST36VF1601 writes (Program or Erase) with a 2.7-3.6V power supply. The SST36VF1601 device conforms to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST36VF1601 device provides a typical Word-Program time of 14 sec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST36VF1601 device has on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST36VF1601 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST36VF1601 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST36VF1601 significantly improves performance and reliability, while lowering power consumption. The SST36VF1601 inherently uses less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST36VF1601 also improves flexibility while lowering the cost for program, data, and configuration storage applications.
(c)2001 Silicon Storage Technology, Inc. S71142-06-000 11/01 373 1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Concurrent SuperFlash and CSF are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST36VF1601 is offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pinouts. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).
Word-Program Operation
The SST36VF1601 is programmed on a word-by-word basis. Before programming, one must ensure that the sector, in which the word which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 10 s. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Concurrent Read/Write Operation
Dual bank architecture of SST36VF1601 device allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. CONCURRENT READ/WRITE STATE
Bank 1 Read Read Write Write No Operation No Operation Bank 2 No Operation Write Read No Operation Read Write
Sector- (Block-) Erase Operation
The Sector- (Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST36VF1601 offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.
Note: For the purposes of this table, write means to perform Block-, Sector-, or Chip-Erase or Word-Program operations as applicable to the appropriate bank.
Read Operation
The Read operation of the SST36VF1601 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data on the output pins.
Chip-Erase Operation
The SST36VF1601 provides a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the "1" state. This is useful when the device must be quickly erased.
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2
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 22 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling (DQ7) timing diagram and Figure 20 for a flowchart. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ7 becomes true data.
Write Operation Status Detection
The SST36VF1601 provides one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 20 for a flowchart. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ6 no longer toggles.
Data Protection
The SST36VF1601 provides both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Ready/Busy# (RY/BY#)
The SST36VF1601 includes a Ready/Busy# (RY/BY#) output signal. RY/BY# is actively pulled low while during an internal Erase or Program operation is in progress. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull up resistor. RY/ BY# is high impedance whenever CE# is high or RST# is low. There is a 1 s bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after RY/BY# goes high.
Hardware Block Protection
The SST36VF1601 provides a hardware block protection which protects the outermost 4 KWord in the larger bank. The block is protected when WP# is held low. See Figure 1 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed.
Data# Polling (DQ7)
When the SST36VF1601 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 16). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 15). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.
sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the device and manufacturer. For details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Word Manufacturer's ID Device ID SST36VF1601 0001H 2761H
T1.1 373
Software Data Protection (SDP)
The SST36VF1601 provides the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST36VF1601 is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 can be VIL or VIH, but no other value during any SDP command sequence.
Data 00BFH
0000H
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for the software command code, Figure 14 for timing waveform and Figure 21 for a flowchart.
Common Flash Memory Interface (CFI)
The SST36VF1601 also contains the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H in the last byte
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Memory Address
Address Buffers
(4 KWord Sector Protection) SuperFlash Memory 12 Mbit Bank
RST# CE# WP# WE# OE# RY/BY#
373 ILL B37.5
SuperFlash Memory 4 Mbit Bank Control Logic I/O Buffers DQ15 - DQ0
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block 31 Block 30 Block 29
Bank 2 Bank 1
Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1
4 KWord Sector Protection (4- 1 KWord Sectors)
Block 0
373 ILL F38.2
FIGURE 1: SST36VF1601, 1 MBIT
(c)2001 Silicon Storage Technology, Inc.
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CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RST# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard Pinout Top View Die Up
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
373 ILL F01b.3
FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM
X
20MM)
TOP VIEW (balls facing down)
SST36VF1601
6 5 4 3 2 1
A13 A9
A12 A14 A8 A10
A15 A16
NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 NC DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS
373 ILL F01a.7
WE# RST# NC
RY/BY# WP# A18
A7 A3
A17 A4
A6 A2
A
B
C
D
E
F
G
H
FIGURE 3: PIN ASSIGNMENTS FOR 48-BALL TFBGA (8MM
X
10MM)
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE 2: PIN DESCRIPTION
Symbol A19-A0 Name Address Inputs Functions To provide memory addresses. During Sector-Erase and Hardware Sector Protection, A19-A10 address lines will select the sector. During Block-Erase A19-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers To control the Write operations To reset and return the device to Read mode To output the status of a Program or Erase Operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. To protect and unprotect the bottom 4 sectors from Erase or Program operation. To provide 2.7-3.6V power supply voltage Unconnected pins
T2.6 373
DQ15-DQ0
Data Input/output
CE# OE# WE# RST# RY/BY#
Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy#
WP# VDD VSS NC
Write Protect Power Supply Ground No Connection
TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH Manufacturer's ID (00BFH) Device ID2
T3.6 373
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z / DOUT High Z / DOUT
Address AIN AIN Sector or block address, XXH for Chip-Erase X X X See Table 4
1. X can be VIL or VIH, but no other value. 2. Device ID = 2761H
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software ID Entry5,6 CFI Query Entry Software ID Exit/ CFI Exit
1. 2. 3. 4.
1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 AAH AAH AAH AAH AAH AAH AAH
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 80H 90H 98H F0H
4th Bus Write Cycle Addr1 WA3 5555H 5555H 5555H Data2 Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H
6th Bus Write Cycle Addr1 SAX4 BAX4 5555H Data2 30H 50H 10H
T4.4 373
Address format A14-A0 (Hex), Addresses A19- A15 can be VIL or VIH, but no other value, for the Command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence WA = Program word address SAX for Sector-Erase; uses A19-A10 address lines BAX for Block-Erase; uses A19-A15 address lines 5. The device does not remain in Software Product Identification mode if powered down. 6. With A19-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0 = 0 SST36VF1601 Device ID = 2761H, is read with A0 = 1
TABLE 5: CFI QUERY IDENTIFICATION STRING1
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T5.0 373
1. Refer to CFI publication 100 for more details.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION
Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Word-Program 2N s (24 = 16 s) Typical time out for min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Word-Program 2N times typical (21 x 24 = 32 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.0 373
TABLE 7: DEVICE GEOMETRY INFORMATION
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 003FH 0000H 0000H 0001H Data Device size = 2N Bytes (15H = 21; 221 = 2 MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 8 x 256 Bytes = 4 KByte/sector (0008H = 8) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001FH = 31) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.3 373
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA OPERATING RANGE:
Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C
OF
VDD 2.7-3.6V 2.7-3.6V
AC CONDITIONS
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 17 and 18
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits Symbol IDD Parameter Active VDD Current Read Program and Erase Concurrent Read/Write ISB IRT ILI ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Reset VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD VDD-0.3 0.2 35 40 75 20 20 1 1 0.8 0.3 mA mA mA A A A A V V V V V V CE#=VIHC, VDD=VDD Max RST# = VSS 0.3V VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T8.6 373
Min
Max
Units
Test Conditions Address input=VIL/VIH, at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=VIL, OE#=VIH
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T9.2 373
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE
Parameter CI/O
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 10 pF 10 pF
T10.0 373
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T11.1 373
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST36VF1601-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Pin Low to Read Mode 0 500 50 150 0 0 20 20 Min 70 70 70 35 Max Units ns ns ns ns ns ns ns ns ns ns ns s
T12.9 373
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH TDS TDH TSE TBE TSCE TBY1 TBR
1 1
Parameter Word-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase RY/BY# Delay Time Bus Recovery Time
Min 0 40 0 0 0 10 40 40 30 30 30 0
Max 20
Units s ns ns ns ns ns ns ns ns ns ns ns ns
TIDA1
150 25 25 100 90 1
ns ms ms ms ns s
T13.6 373
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
TRC ADDRESSES
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
373 ILL F22.1
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
FIGURE 4: READ CYCLE TIMING DIAGRAM
TBP ADDRESSES 5555 TAH TCP WE# TAS OE# TCH CE# TCS RY/BY# DQ15-0 TDS TDH XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) VALID TBY TBR TCPH 2AAA 5555 ADDR
373 ILL F23.11
Note: X can be VIL or VIH, but no other value.
FIGURE 5: WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
TBP ADDRESSES 5555 TAH TCP CE# TAS OE# TCH WE# TCS RY/BY# DQ15-0 TDS TDH XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) VALID TBY TBR TCPH 2AAA 5555 ADDR
373 ILL F24.10
Note: X can be VIL or VIH, but no other value.
FIGURE 6: CE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESSES TCE CE# TOEH OE# TOE WE# TBR DQ7 DATA# DATA# DATA# VALID DATA TOES
373 ILL F41.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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15
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
ADDRESSES TCE CE# TOEH OE# TOE
WE# TBR DQ6
TWO READ CYCLES WITH SAME OUTPUTS
VALID DATA
373 ILL F42.1
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE# TBY RY/BY# TBR
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX10 SW5
VALID
373 ILL F27.6
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) X can be VIL or VIH, but no other value.
FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc. S71142-06-000 11/01 373
16
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA BAX
TBE
CE#
OE# TWP WE# TBY RY/BY# TBR
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX50 SW5
VALID
373 ILL F28.8
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE# TBY TBR
RY/BY#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX30 SW5
VALID
373 ILL F29.8
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address X can be VIL or VIH, but no other value.
FIGURE 11: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESSES 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2
373 ILL F30.6
TIDA
TAA 00BF
Device ID
Device ID = 2761H for SST36VF1601 Note: X can be VIL or VIH, but no other value.
FIGURE 12: SOFTWARE ID ENTRY
AND
READ
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESSES 5555 2AAA 5555
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX98 SW2
373 ILL F31.2
TIDA
TAA
Note: X can be VIL or VIH, but no other value.
FIGURE 13: CFI ENTRY
AND
READ
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESSES 5555 2AAA 5555
DQ15-0
XXAA
XX55
XXF0 TIDA
CE#
OE# TWP WE# TWPH SW0 SW1 SW2
373 ILL F32.4
Note: X can be VIL or VIH, but no other value.
FIGURE 14: SOFTWARE ID EXIT/CFI EXIT
RY/BY# 0V RST# TRP
CE#/OE# TRHR
373 ILL F43.1
FIGURE 15: RST# TIMING (WHEN
NO INTERNAL OPERATION IS IN PROGRESS)
TRY RY/BY# RST#
TRP CE# OE#
373 ILL F44.3
TBR
FIGURE 16: RST# TIMING (DURING SECTOR(c)2001 Silicon Storage Technology, Inc.
OR
BLOCK-ERASE
19
OPERATION)
S71142-06-000 11/01 373
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
373 ILL F14.3
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
373 ILL F15.1
FIGURE 18: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
373 ILL F33.3
Note: X can be VIL or VIH, but no other value.
FIGURE 19: WORD-PROGRAM ALGORITHM
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read word
Read DQ7
Program/Erase Completed
Read same word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
373 ILL F34.0
FIGURE 20: WAIT OPTIONS
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
CFI Query Entry Command Sequence
Software Product ID Entry Command Sequence
Software ID Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal operation
373 ILL F35.2
Note: X can be VIL or VIH, but no other value.
FIGURE 21: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
Note: X can be VIL or VIH, but no other value.
373 ILL F36.2
FIGURE 22: ERASE COMMAND SEQUENCE
(c)2001 Silicon Storage Technology, Inc.
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24
16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 XX Suffix2 XX Package Modifier K = 48 balls Package Type B = TFBGA (8mm x 10mm) E = TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Bank Split 1 = 12 Mbit + 4 Mbit Device Density 160 = 1M x16 Voltage V = 2.7-3.6V
SST36VF1601 - XXX
Valid combinations for SST36VF1601 SST36VF1601-70-4C-EK SST36VF1601-70-4E-EK
Note:
SST36VF1601-70-4C-BK SST36VF1601-70-4E-BK
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2001 Silicon Storage Technology, Inc.
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16 Mbit Concurrent SuperFlash SST36VF1601
Data Sheet
PACKAGING DIAGRAMS
1.05 0.95 Pin # 1 Identifier 0.50 BSC
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL
1.20 max. 0.70 0.50
20.20 19.80 0- 5
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-tsop-EK-ILL.7
0.70 0.50
1mm
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK
X
20MM
BOTTOM VIEW TOP VIEW
10.00 0.20 5.60 0.80
8 7 6 5 4 3 2 1
0.80 HGFEDCBA 4.00 8.00 0.20
8 7 6 5 4 3 2 1
0.30 0.05 (48X) A1 CORNER
ABCDEFGH A1 CORNER 1.10 0.10
SIDE VIEW
48ba-tfbga-BK-8x10-300mic-ILL.10
0.15 SEATING PLANE 0.21 0.05
1mm
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.1 (.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM SST PACKAGE CODE: BK
X
10MM
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. S71142-06-000 11/01 373
26

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